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ml2722 900mhz low - if 1.5mbps fsk transceiver final datasheet ds2722 - f - 05 decemb er 2003 general description the ml2722 is a fully integrated 1.5mbps frequency shift keyed (fsk) transceiver that operates in the unlicensed 900mhz ism frequency band. the device has been optimized for digital cordless telephone applications and includes all the f requency generation, receive and transmit functions. automatically adjusted filters eliminate mechanical tuning. the transmitter generates a - 1 dbm fsk output signal. the single conversion low - if receiver has all the sensitivity and selectively advantages of a traditional super - heterodyne without requiring costly, bulky external filters, while providing the integration advantages of direct conversion. the phase locked loop (pll) synthesizer is completely integrated, including the voltage controlled oscillat or (vco), tuning circuits, and vco resonator. this allows the ml2722 to be used in frequency hopped spread spectrum (fhss) applications. the ml2722 contains internal voltage regulation. it also contains pll and transmitter configuration registers. the devi ce can be placed in a low power standby mode for current sensitive applications. it is packaged in a 32tqfp. pin configuration vcc5 trfo rvcc4 rrfi gnd gnd gnd gnd 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 xcen rxon paon en data clk tpc/tpq vss ref rvcc1 qpo gnd vcc2 rvcc3 vtune gnd dout vdd din rvcc7 rssi/tpi rvcc6 vbg gnd ordering information part number temperature range package publication ml2722dh - 10 o c to +60 o c 32 pin tqfp 7mm body ds2722 - f - 05 features single chip ism band 900mhz radio transceiver with - 1 dbm transmit output power 1.5mbps maximum data rate typical receiver sensitivity: - 95dbm at 12.5% cer fully integrated frequency synthesizer with internal vco resonator automatic filter calibration: requires no mechanical tuning adjustments during manufacturing low if receiver: no external if filters required control outputs correctly sequence and control external pa 3 - wire control interface analog rssi output applications 900mhz fsk da ta transceivers - digital cordless phones - wireless streaming media - wireless pc peripherals block diagram
ml2722 ds2722 - f - 05 final da tasheet december 2 003 2 table of contents general description ................................ ................................ ................................ ................................ ............ 1 pin configuration ................................ ................................ ................................ ................................ ................. 1 ordering information ................................ ................................ ................................ ................................ ......... 1 features ................................ ................................ ................................ ................................ ................................ .... 1 applicatio ns ................................ ................................ ................................ ................................ ............................. 1 block diagram ................................ ................................ ................................ ................................ ........................ 1 table of contents ................................ ................................ ................................ ................................ ................ 2 change log ................................ ................................ ................................ ................................ .............................. 2 simplified applicati ons diagram ................................ ................................ ................................ ...................... 3 electrical character istics ................................ ................................ ................................ ............................. 4 pin descriptions ................................ ................................ ................................ ................................ .................... 7 functional descripti on ................................ ................................ ................................ ................................ .... 13 modes of operation ................................ ................................ ................................ ................................ ........... 15 data interfaces ................................ ................................ ................................ ................................ .................... 18 control interfaces a nd register descript ions ................................ ................................ ................... 20 physical dimensions (inches/millimeters) ................................ ................................ ................................ . 27 ordering information ................................ ................................ ................................ ................................ ....... 27 warranty ................................ ................................ ................................ ................................ ................................ 28 change log version date author changes/comments ds2722 - f - 03 9/26/03 derby reformatted and updated from f02 ds2 722 - f - 04 10/13/03 derby error on page 21 table 5 ? divide ratio = fc / 0.512 ds2722 - f - 05 12/12/03 derby some graphics printed poorly to pdf.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 3 simplified applicati ons diagram image reject mixer ml2722 if demod circuits control logic pll baseband ic rrfi dout din rssi ref clk, data, en xcen, rxon 2 vcc5 tx data filter loop filter battery and protection circuits vtune qpo quadrature divide by 2 1.83ghz vco tx rf buffer pa trfo 3 switch drivers rf pin diode switch antenna matching network filter lna paon, tpc 2 figure 1. simplified applicati on diagram
ml2722 ds2722 - f - 05 final da tasheet december 2 003 4 electrical character istics absolute maximum rat ings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implie d. vdd, vcc5 ................................ ................................ ................................ ................................ ................................ . 6.0 v vss, gnd ................................ ................................ ................................ ................................ .............................. 0 0.3v junction temperature ................................ ................................ ................................ ................................ ............... 150c storage temperature range ................................ ................................ ................................ ....................... - 65c to 150c lead temperature (soldering, 10s) ................................ ................................ ................................ .......................... 260c operating conditions normal temperature range ................................ ................................ ................................ .......................... - 10c to 60c vcc5 range ................................ ................................ ................................ ................................ ................... 2.7v to 4.5v thermal resistance ( q ja ) ................................ ................................ ................................ ................................ .... 100c/w vdd range (vcc5 = vdd) ................................ ................................ ................................ ............................ 2.7v to 4.5v unless otherwise specified, vcc5 & vdd = 2.7v to 3.8v, t a = operating temperature range (note 1) 6.144 or 12.288mhz reference frequency input parameter conditions min typ max units power consumption i stby al l circuits, standby mode 10 100 m a i rx, i tx receive or transmit mode t a = 25c, vcc5 & vdd = 3.3v 30 50 63.5 ma i rx, i tx receive or transmit mode t a = operating temperature range 20 50 70 ma synthesizer f c lo output frequency in 512 khz steps 902 9 28 mhz f n phase noise at driver output 1.2 mhz 3 mhz >7 mhz vco phase locked, loop bandwidth 50khz. discontinuities, other than reference spurs, not allowed. - 100 - 120 - 125 dbc/hz f ref lo pll reference frequency at phase detector pll main divi der input is at 1.83 ghz 1.024 mhz n lo division range integer pll divider limits 1024 4093 count i p lo charge pump sink/source current 5.5 ma t tx2rx lo lock up time for transmit/receive frequency change from rxon asserted 50 m s t fh lo lock up time for channel switch from en asserted, any channel change in 902 to 928 mhz band 100 m s t wake lo lock up time from sleep from xcen, pll dividers programmed 240 m s v fref reference signal input level 6.144 or 12.288mhz sine wave, capacitively coupl ed 2.0 3.0 vp - p
ml2722 ds2722 - f - 05 final da tasheet december 2 003 5 receiver z in receiver rf impedance f c =915 mhz 17 - j50 w nf receiver rf noise figure f c =915 mhz 9 db dr rx data rate fsk modulation, fdev=+/ - 460khz 1.536 mbps s input sensitivity for better than 12.5% cer - 95 dbm bw rx bandwi dth 3db nominal 770 khz p imax maximum rx rf input <12.5% cer at 1.536mchip/s 8 dbm i ip3 receiver input ip3 test tones 2 and 4 channels away - 12 dbm lo leakage at rxi - 80 dbm irr receive rf mixer image rejection measured at 3.5mhz offset 35 db adjacent channel rejection - 80dbm wanted signal <12.5% cer (a single interferer with 2gfsk modulation to give a - 20dbc bandwidth of 1.5mhz) 1 channel 2 channels 3 or more channels 15 40 45 db receiver settling time rxon high to va lid data 120 m s if filters f ifc if filter center frequency after automatic filter alignment 1.024 mhz bw if if filter 3db bandwidth after automatic filter alignment 1405 khz limiter, agc, and fm demodulator t ovld recovery from overload from 0dbm at input 5 12 m s eb/no for 12.5% cer 3 db co - channel rejection, 12.5% cer - 80 dbm, modulated with 1.536mbps gfsk, bt=0.5, prbs data 4 db am tolerance for 12.5% or better cer - 80 dbm wanted signal, am modulation depth at 100 khz rate 90 % rs si performance t rrssi rssi rise time: < - 100dbm to - 15dbm into the if mixer 20 pf load, 20% to 80% 1 5.3 10 m s t frssi rssi fall time: < - 15dbm to < - 100dbm into the if mixer 20 pf load, 20% to 80% 1 4.4 10 m s v rsmx rssi maximum voltage - 15dbm in 2.2 2.8 v v rsmn rssi minimum voltage no signal 0.05 v g rsmid rssi sensitivity, mid range 28 35 42 mv/db p rsmx rssi maximum signal sensitivity is >50% mid range - 20 dbm p rsmn rssi minimum signal sensitivity is >50% mid range - 95 dbm rssi accuracy me asured at - 40dbm input power 1.5 1.9 2.1 v
ml2722 ds2722 - f - 05 final da tasheet december 2 003 6 transmit rf buffer p out driver amplifier output power when matched into 50 w - 4.5 - 1.0 +2.0 dbm driver amplifier output return loss 902 to 928 mhz 14 db transmit modulation f dev modulation deviation, internal vco 5 consecutive 1 or 0 bits 400 460 560 khz f os modulation center frequency offset between 50 m s and 10 ms after paon high - 100 +100 khz transmit data filter bw tx transmit data filter bandwidth 3db bandwidth 1.4 mhz interface logic leve ls v ih input high voltage never exceed vdd 0.75 * vdd vdd v v il input low voltage 0.25 * vdd v i b input bias current - 5 0 5 m a c in input capacitance measured at 1mhz 4 6 pf v oh dout high voltage sourcing 0.1 ma typical value assumes 3.3v vdd vdd - 0.6 3.08 v v ol dout low voltage sinking 0.1 ma 0.18 0.6 v interface timing t rx2pa rx to tx switching time time from rxon low to paon high 62.5 70 m s t tx2en tx to rx switching time time from rxon high to receiver enabled 72 80 m s t rxen channel switching time time from write to pll tuning register (en high) to receiver enabled 320 342 m s t xcen chip enable time from xcen hig h to receiver enabled with continuous reference applied 320 342 m s note 1: limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 7 pin descriptions pin signal name i/o function diagram power & ground 8 vss i (d igital) ground for digital i/o circuits and control logic. 10 rvcc1 o (analog) dc power supply decoupling point for the pll dividers, phase detector, and charge pump. this pin is connected to the output of the regulator and to the pll supplies. there mus t be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator. 12 gnd i (analog) ground for the pll dividers, phase detector, and charge pump. 13 vcc2 i (analog) dc power supply input to the vco voltage regulator. m ust be connected to rvcc6 (pin 27) or rvcc7 (pin 29) via decoupling network. 14 rvcc3 o (analog) dc power supply decoupling point for the vco. connected to the output of the vco regulator. a capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. 16 gnd i (analog) dc ground for vco and lo circuits. 17 gnd i (analog) signal ground for rf small signal circuits. pins 17, 18, and 19 should have short, direct connections to each other and additional co nnections to ground. 18 gnd i (analog) ground return for the receive rf input. 19 gnd i (analog) signal ground for the receive mixers. 20 gnd i (analog) dc and signal ground for the transmit rf output buffer. 22 rvcc4 o (analog) dc power supply dec oupling point for the lo chain. connected to the output of a regulator. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator. 24 vcc5 i (analog) dc power supply input to voltage regulators and unregu lated loads. vcc5 is the main (or master) analog vcc pin. there must be a capacitor to ground from this pin to decouple (bypass) noise and to stabilize the regulator. 25 gnd i (analog) dc ground to if, demodulator, and data slicer circuits. 27 rvcc6 o (analog) dc power supply decoupling point for quadrature mixer and if filter circuits. a capacitor must be tied between this pin and ground to decouple (bypass) noise
ml2722 ds2722 - f - 05 final da tasheet december 2 003 8 pin signal name i/o function diagram and to stabilize the regulator. 29 rvcc7 o (analog) dc power supply decoupling point fo r if, demodulator, and data slicer circuits. a capacitor must be tied between this pin and ground to decouple (bypass) noise and to stabilize the regulator. 31 vdd i (digital) dc power supply input to the interface logic and control registers. this suppl y is not connected internally to any other supply pin, but its voltage must be less than or equal to the vcc5 supply and greater than 2.7 v. a capacitor must be tied between this pin and ground to decouple (bypass) noise. transmit/receive 21 rrfi i (ana log) receive rf input. nominal impedance at 902 to 928 mhz is 17 - 50j w with a simple matching network required for optimum noise figure. this input is to the base of an npn transistor and should be ac coupled. (pin 24) (pin 8) vss gnd rrfi vcc5 0.7v vcc5 vss 4k 21 18 8 24
ml2722 ds2722 - f - 05 final da tasheet december 2 003 9 pin signal name i/o function diagram 23 trfo o (analog ) transmit rf output. this output is an emitter follower and should be ac coupled. vcc5 13 12ma trfo vss 8 23 24 w data 30 din i (cmos) transmit data input. drives the transmit pulse shaping circuits. serial digital data on this pin becomes fsk modulation on the transmit rf output. the logic timing on this pin controls data timing. internal circuits determine the modulation deviation. this is a standard cmos input referenced to vdd and vss. 1 vss xcen vdd rxon din 2 30 31 8 32 dout o (cmos) serial digital output after demodulation, chip ra te filtering and center data slicing. a cmos level output (vss to vdd) with controlled slew rates. a low drive output designed to drive a pcb trace and a cmos logic input while generating minimal rfi. in digital test modes this pin becomes a test access po rt controlled by the serial control bus. 31 vss vdd 250 w 32 dout 8
ml2722 ds2722 - f - 05 final da tasheet december 2 003 10 pin signal name i/o function diagram mode control and int erface lines 1 xcen i (cmos) enables the bandgap reference and voltage regulators when high. with xcen low the device consumes only leakage current in standby mode w hen low. xcen low also preserves register contents and allows register writes. this is a cmos input, and the thresholds are referenced to vdd and vss. 1 vss xcen vdd rxon din 2 30 31 8 2 rxon i (cmos) switches the transceiver between transmit and receive modes. circuits are powered up a nd signal paths reconfigured according to the operating mode. this is a cmos input, and the thresholds are referenced to vdd and vss. 1 vss xcen vdd rxon din 2 30 31 8 3 paon o (cmos) enables the off - chip pa at the correct times in a transmit slot. goes high when transmit rf is present at trfo; goes low 5 s before transmit rf is removed from trfo. has interlock logic to shut down the pa if the pll does not lock. 31 vss vdd 3 paon 8
ml2722 ds2722 - f - 05 final da tasheet december 2 003 11 pin signal name i/o function diagram 7 tpc/tpq o (open drain) transmit power control output. this open - drain output is pulled low when the tpc bit in serial register #0 is set. transitions on tpc are synchronized to the falling edge of rxon. in analog test modes, this pin and the rssi output become test access points controlled by the serial control bus. 31 vss vdd 100 7 tpc/tpq 8 tpq mux vss 8 tpc mux tpc w 9 ref i input for the 12.288 mhz or 6.144 mhz reference frequency. this input is used as the reference frequency for the pll and as a calibration frequency for the on - chip filters. this is a self - biased cmos input that is designed to be driven either by an ac - coupled sine wave. 9 vss ref vcc5 24 8 40k 40k 11 qpo o charge pump output of the phase detector. this is connected to the external pll loop filter. 10 vss r vcc1 11 qpo 8 vcc5 24
ml2722 ds2722 - f - 05 final da tasheet december 2 003 12 pin signal name i/o function diagram 15 vtune i vco tuning voltage input from the pll loop filter. this pin is very sensitive to noise coupl ing and leakage currents. 26 vbg o internal bandgap reference voltage. decoupled to ground with a 220nf capacitor. 28 rssi/tpi o buffered analog rssi output with a nominal sensitivity of 35mv/db. an rf input signal range of ? 95 to ? 20 dbm gives an rs si voltage output of zero to 2.7 v. 24 vss vcc5 100 w 28 rssi/tpi 8 tpi mux rssi mux rssi op amp serial bus signals 4 en i (cmos) enable pin for the three - wire serial control bus that sets the operating frequency and programmable options. the control registers are loaded on a low - to - h igh transition of the signal. serial control bus data is ignored when this signal is high. this is a cmos input, and the thresholds are referenced to vdd and vss. 5 data i (cmos) serial control bus data. 16 - bit words, which include programming data and the two - bit address of a control register. this is a cmos input, and the thresholds are referenced to vdd and vss. 6 clk i (cmos) serial control bus data is clocked in on the rising edge when en is low. this is a cmos input; the thresholds are reference d to vdd and vss. 31 vss vdd 5.5k 4 en 8 1.7p 5 data 6 clk 13 vss vcc2 3.7k 15 vtune 8 1.25v 13 vss vcc2 3.7k 15 vtune 8 1.25v
ml2722 ds2722 - f - 05 final da tasheet december 2 003 13 functional descripti on the ml2722 enables the design and manufacture of low - cost, high - performance fsk transceivers. it can also be used as a 900mhz digital cordless telephone transceiver. integral to the ml2722 is a low - if receiver w hose lo port is driven from an internal synthesizer. included are image rejection if filters, limiters, discriminator, data slicers, and baseband low - pass data filters. it also contains internal voltage regulators to protect critical circuits from power su pply noise and transmit modulation circuits. the ml2722 is designed to transmit and receive 1.536m chips per second in 2.048mhz spaced channels in the 902 to 928mhz ism band. a single synthesizer is used for both the receiver and the fsk transmitter. the phase locked loop (pll) is completely integrated, including the voltage controlled oscillator (vco), tuning circuits, and vco resonator. the ml2722 has an internal control interface that programs the synthesizer, the mode of operation, the external lna an d pa, and provides a convenient and flexible interface to various baseband processors. for power level monitoring an rssi block is included. in receive mode , the ml2722 is a single conversion low if receiver. the demodulation is followed by a matched bit r ate filter and a data slicer. the sliced data is provided to a baseband chip for despreading. all channel filtering and demodulation is performed using active filters, which are automatically aligned. a matched bit rate filter and a data slicer follow the demodulator. the sliced data is provided at the dout pin. in transmit mode , the ml2722 uses the receive mode vco and frequency division, with a driver amplifier providing typically - 1 dbm output to feed the power amplifier. the pll frequency synthesizer l oop is opened during the transmit time slot, and the vco is directly modulated by low - pass filtered circuits from the internal modulation filter. the ml2722 uses multiple voltage regulators to protect sensitive internal circuits from power supply noise. se parate regulators supply the pll dividers, rf circuits and if circuits. each of these regulators takes its power from vcc5, and supplies power internally to its respective rvccn pin. external capacitors are required at each rvccn pin to decouple the output s of the internal regulators. the vco regulator takes its power from the vcc2 pin which is normally connected to the rvcc6 (pin 27) or rvcc7 (pin 29). an external decoupling capacitor is also used on the internal bandgap voltage reference to improve the no ise performance of the regulators. the integrated pll frequency synthesizer includes a fully integrated vco, prescaler, phase detector and charge pump. the reference frequency is generated from the incoming signal at the ref pin, which can be either 6.1 44mhz or 12.288mhz. the loop filter is external to allow customers to optimize their loop bandwidth to their system?s lock time and in - band phase noise requirements. this frequency - agile synthesizer allows the ml2722 to be used in frequency hopped spread spectrum (fhss) applications with nominal channel spacing of 2.048mhz. carrier frequency is programmed via the configuration registers and 3 - wire serial interface. the vco tank circuit (inductor and varactor) is fully integrated. example 38khz loop filter 2.2nf 470 w 22nf rvcc3 qpo vtune
ml2722 ds2722 - f - 05 final da tasheet december 2 003 14 23 trfo address decode lo 6 - bit swallow counter prescaler control lock detect lo 6 - bit counter prescaler 32 / 33 reference divider lo phase/ frequency detector lo charge pump control logic tx data filter quadrature divide by 2 1 xcen 2 rxon 3 paon 30 din 4 en 5 data 6 clk 28 rssi/tpi 9 ref 7 tpc/tpq data slicer data filter demod if filter test mux filter align rssi 32 dout tx rf buffer i q i q 15 vtune 11 qpo 8 vss 12 gnd 17 gnd 16 gnd 19 gnd 20 gnd 18 gnd 25 gnd 21 rrfi 24 vcc5 dc regulators 22 rvcc4 14 rvcc3 10 rvcc1 31 vdd 29 rvcc7 27 rvcc6 13 vcc2 26 vbg rx quadrature mixers 1.83ghz vco li miter figure 2. ml2722 block diagram
ml2722 ds2722 - f - 05 final da tasheet december 2 003 15 modes of operation overview standby: all circuits powered down, except the control interface (static cmos) receive: receiver circuits active transmi t: pll open loop, modulated rf output available from the ic the two operational modes are receive and transmit. they are set by the rxon control (pin 2). xcen (pin 1) is the chip enable/disable and can be set for standby operation. the relationship betwee n the parallel control lines and the mode of operation of the ic is given in table 1 . xcen rxon mode transceiver mode 0 x standby control interfaces active, all other circuits powered down 1 1 receive receiver time slot 1 0 tran smit transmit time slot table 1 : modes of operation m ode c ontrol the ml2722 is intended for use in tdd and tdma radios in battery - powered equipment. to minimize power consumption it is designed to switch rapidly from a low power m ode (standby) to receive or transmit. the ml2722 can also make a quick transition from receive to transmit for tdd operation. prior to transmitting or receiving, time should be allowed for the pll to lock up and for the filters to be aligned. when the ml27 22 is operated in single - carrier tdd mode, the lo is automatically shifted by the second (low) if frequency when the device is switched between receive and transmit modes. ml2722 carrier frequency can be changed (hopped) between transmissions. carrier freq uency (channel) is modified in the ml2722 by writing a corresponding new value to the pll frequency register. receive the ml2722 uses a single - conversion heterodyne receiver with a nominal if of 1.024mhz. the signal flow in receive mode is from the rf inpu t, through an image reject quadrature mixer, limiter, frequency - to - voltage converter, data filter, and data slicer where the digital nrz data is available at the dout pin. a 20db step agc extends the dynamic range of the receiver. the ml2722 receive chain is a low if receiver using advanced integrated radio techniques to eliminate external if filters and minimize external rf filter requirements. the precision filtering and demodulation circuits give improved performance over conventional radio design using external filters while providing integration comparable to advanced direct conversion radio designs.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 16 receive signal strength indication (rssi) rssi is an indication of field strength. it is typically used to control transmit power to conserve battery lif e. it may also be used to determine if a given channel is occupied (see figure 3). rssi voltage vs rf level 0.00 0.50 1.00 1.50 2.00 2.50 3.00 -100 -90 - 80 -70 - 60 -50 - 40 -30 - 20 -10 receive rf level (dbm) rssi voltage figure 3. typical rssi response automatic filter alignment when the ml2722 is placed in receive mode, it automatically tunes all the internal filters using the reference f requency from the ref pin. this self - calibration sets: discriminator center frequency if filter center frequency and bandwidth receiver data low - pass filter bandwidth transmit data low pass filter bandwidth transmit mode in transmit mode, the vco is direc tly modulated with filtered fsk transmit data. the ml2722 transmitter is a 2 - fsk transmitter using a directly modulated open loop vco. the ml2722 design supports transmit time slot lengths up to 10ms, and the time required to set up the transmitter for a n ew time slot (txcal mode) is 62.5s.this type of transmitter is simple, low power, and well suited to a time - time slotted system. the transmitter uses the stored vco tuning voltage on the pll loop filter to set the vco frequency for the duration of the tra nsmitter time slot. the modulation is introduced through a second vco tuning port. this modulation port has a much lower tuning sensitivity than the main tuning port in order to produce the 460khz fsk deviation. compensation circuits stabilize the modulat ion deviation over the vco tuning range, and internal logic manages the correct transition from txcal to transmit mode. the operating cycle of the transmitter starts with the falling edge of rxon. in the first 62.5 s after the falling edge of rxon, a calibration mode (txcal) is triggered. the data filter input is zeroed and the pll locks the vco frequency to the desired rf channel center frequency. a cw signal at the selected rf channel frequency comes out of the tr ansmit rf output. when the internally generated pllen control line changes state, the transmitter starts its transition to transmit mode. the pll charge pump is disabled, leaving the pll loop filter to hold the correct tuning voltage for this channel. the data formatter injects an nrz bipolar data waveform into the transmit data filter. the transmit data filter bandlimits this waveform, and feeds it to the modulation compensation circuits. these scale the modulation voltage (depending on the vco tuning volt age) and drive the vco tuning port with the scaled, filtered modulation. the voltage on the modulation port swings above and below its central value to produce 2 - fsk modulation on the vco. the modulation filtering is sufficient to meet the fcc occupied ban dwidth and out - of - band emissions requirements, and does not introduce significant isi (inter symbol interference). the transmit modulation filter is automatically tuned during the first part of every rx and tx time (rxcal&txcal) to remove the need for prod uction alignment. when the chip is first powered up, the tuning information is reset to mid - range. the ml2722 should then be enabled with rxon high. the rising edge on xcen will trigger a complete calibration of all the on chip filters, which takes 320s. this ensures the modulation filters are aligned to prevent unwanted spurious emissions.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 17 prior to transmitting the pll must tune to the intended rf center frequency of the transmission. this occurs in txcal mode. the transmit modulation is disabled and any input on the din (pin 30) is ignored. the transmit output buffer is enabled during txcal mode. to prevent spurious emissions due to the pll locking, any external antenna switch or pa should be disabled during txcal mode. for optimum performance we recommen d that the second harmonic level reflected back into the output trfo (pin 23), be less than ? 30dbm. phase locked loop (pll) and channel selection the pll synthesizes channel frequencies to a 512khz resolution, which is more finely spaced than the 1.536mhz signal bandwidth. non - overlapping channels are spaced by 2.048mhz where the if filter and image reject mixer give a typical adjacent channel rejection of 25db. there are twelve non - overlapping channels in the 902 to 928mhz ism band (see table 2). channel f requency in mhz 1 903.680 2 905.728 3 907.776 4 909.824 5 911.872 6 913.920 7 915.968 8 918.016 9 920.064 10 922.112 11 924.160 12 926.208 table 2. non - overlapping channel frequencies the lo pll is programmed via a 3 - wire serial control bus. p rogram words are clocked in on the data line (pin 5) by the clk (pin 6), and loaded into the dividers or control circuits when en (pin 4) is asserted. there is no check for errors in the program words. once loaded, register contents are preserved while vdd is present. the register status and operation is independent of the mode of operation of the pll. the reference signal from an external crystal oscillator at either 6.144mhz or 12.288mhz is fed to a programmable reference divider. the 1.024mhz reference d ivider output is fed to the lo phase frequency detector. the pll prescaler input comes from the vco at 1.83ghz, so the 1.024mhz comparison frequency gives 512khz frequency resolution at 902 to 928mhz. standby mode in standby the ml2722 transceiver is power ed down. the only active circuits are the control interfaces, which are static cmos to minimize power consumption. the serial control interface (and control registers) remain powered up and will accept and retain programming data as long as the digital sup ply is present. the ml2722 serial control registers should be loaded with control and configuration data before any active mode is selected. the filter alignment registers are reset at power up. test mode the rf to digital functionality of the ml2722 requi res special test mode circuitry for ic production test and radio debugging. a test register, available via the 3 - wire serial interface, controls the test multiplexers.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 18 control interfaces there are two control interfaces: parallel and serial. parallel int erface the parallel interface provides immediate control and monitoring of the ml2722. input signals include: xcen: transceiver enable. places the ml2722 in standby or active (when asserted) modes. rxon: receive on. places an active ml2722 in receive mod e when asserted. ref: reference frequency input output signals include: rssi: received signal strength indicator: indicates the power of the received signal paon: external power amplifier control pin serial interface a 3 - wire serial interface (en, dat a, clk) is used for programming the ml2722 configuration registers, which control device mode, pin functions, pll and reference dividers, internal test modes, and filter alignment. data words are entered beginning with the msb (?big - endian?). the word is d ivided into a leading 14 - bit data field followed by a 2 - bit address field. when the address field has been decoded the destination register is loaded on the rising edge of en. providing less than 16 bits of data will result in unpredictable behavior when e n goes high. data and clock signals are ignored when en is high. when en is low, data on the data pin is clocked into a shift register by rising edges on the clk pin. the information is latched when en goes high. this serial interface bus is similar to tha t commonly found on pll devices. the data latches are implemented in static cmos and use minimal power when the bus is inactive. table 3 and figure 4 provide timing and register programming illustrations.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 19 symbol parameter time ( ns ) t r clock input rise time 15 t f clock input fall time 15 t ck clock period >50 t w minimum pulse width 2000 t d delay from last clock falling edge >15 t se enable setup time to ignore next rising clock >15 t s data - to - clock setup time >15 t h data - to - clock ho ld time >15 table 3. 3 - wire bus timing characteristics clk t s data lsb en t r t f t h t w t ck t se t d msb db13 db11 db0 adr1 adr0 db12 address data (2 bits) register data (14 bits) figure 4. serial bus timing for address and data programming
ml2722 ds2722 - f - 05 final da tasheet december 2 003 20 control interfaces a nd register descript ions register information a unidirectional 3 - wire serial bus sets the ml2722?s transceiver p arameters and programs the pll circuits. programming is performed by entering 16 - bit words into the ml2722 serial interface. three 16 - bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. the three registers are: register 0: pll configuration register 1: channel frequency data register 2: internal test access figure 5 shows a register map. table 4 through table 6 provide detaile d diagrams of the register organization: table 4 and table 5 outline the pll configuration and channel frequency registers, and table 6 displays the filter tuning and test mode register. 14 - bit data 2 - bit address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. res. r es. res. res. res. res. tpc txcl lol rxcl rd0 qpp 0 0 14 - bit data 2 - bit address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. chq11 chq10 chq9 chq8 chq7 chq6 chq5 chq4 chq3 chq2 chq1 chq0 0 1 14 - bit data 2 - bit address res. db13 msb b15 db12 b14 db11 b13 db10 b12 db9 b11 db8 b10 db7 b9 db6 b8 db5 b7 db4 b6 db3 b5 db2 b4 db1 b3 db0 b2 adr1 b1 adr0 b0 res. res. res. res. res. res. res. dtm2 dtm1 dtm0 atm2 atm1 atm0 1 0 figure 5. register organization
ml2722 ds2722 - f - 05 final da tasheet december 2 003 21 data bi t name description use b15 (msb) / db13 reserved reserved b14 / db12 reserved reserved b13 / db11 reserved reserved b12 / db10 reserved reserved b11 / db9 reserved reserved b10 / db8 reserved reserved b9 / db7 reserved reserved b8 / db6 reserved reserved set all bits to 0 (zero) b7 / db5 tpc transmit power control 0: tpc pin high impedance 1: tpc pin pulled to ground b6 / db4 txcl transmit test mode 0: fsk modulation in transmit mode 1: cw (no modulation in transmit mode) b5 / db3 lol pll frequency shift 0: lo shift is 0 hz for transmit, 1.024 mhz for receive 1: lo shift is 1.024 mhz for transmit, 0 hz for receive b4 / db2 rxcl pll mode in normal receive operation 0: pll open loop during receive 1: pll closed loop during receive b3 / db1 rd0 reference frequency select 0: 6.144mhz nominal reference frequency 1: 12.288mhz nominal reference frequency b2 / db0 qpp pll charge pump polarity 0: freq. sig. < freq. ref.; charge pump sources current 1: freq. sig. < freq. ref. ; charge pump sinks cur rent b1 / adb1 adr1 msb address bit adr1 = 0 b0 (lsb) / adb0 adr0 lsb address bit adr0 = 0 table 4. register 0 -- pll configuration register data bit name description use b15 (msb) / db13 reserved b14 / db12 reserved set all bits to 0 (zero) b13 / db11 chq11 b12 / db10 chq10 b11 / db9 chq9 b10 / db8 chq8 b9 / db7 chq7 b8 / db6 chq6 b7 / db5 chq5 b6 / db4 chq4 b5 / db3 chq3 b4 / db2 chq2 b3 / db1 chq1 b2 / db0 ch q0 channel frequency select bits divide ratio = f c / 0.512 b1 / adb1 adr1 msb address bit adr1 = 0 b0 (lsb) / adb0 adr0 lsb address bit adr0 = 1 table 5. register 1 ? channel frequency register
ml2722 ds2722 - f - 05 final da tasheet december 2 003 22 data bit name description use b15 (msb) / db13 reserved b14 / db12 reserved b13 / db11 reserved b12 / db10 reserved b11 / db9 reserved b10 / db8 reserved b9 / db7 reserved b8 / db6 reserved reserved set all bits to 0 (zero) b7 / db5 dtm2 b6 / db4 dtm1 b5 / db3 dtm0 digital test control bits see table 15 b4 / db2 atm2 b3 / db1 atm 1 b2 / db0 atm 0 analog test control bits see table 14 b1 / adb1 adr1 msb address bit adr1 = 1 b0 (lsb) / adb0 adr0 lsb address bit adr0 = 0 table 6. register 2 ? test mode register control register des criptions power - on state all register values are se t to 0 (zero) on power up. power up is defined as occurring when vdd (pin 31) = 2.0v (typical). the register default values are valid after power up. the pll divide ratio and pll configuration registers must be programmed before xcen is asserted for the fi rst time. address and data bits (adr) each of the three registers are identically configured. each is divided into a fourteen (14) bit data field and a two (2) bit address field. the 16 bits are input serially (see figure 5) with the 14 data bits, most sig nificant bit (db13) first followed by the two address bits, most significant bit (adr1) first. the last 16 bits clocked into the ml2722 will be loaded into the specified register. loading less than 16 bits into any register will cause unpredictable device functionality. res bit locations (reserved) bits identified as reserved must always have a logic 0 (zero) value for correct device operation. power - on reset clears all reserved bits to zero. each reserved bit must be programmed to logic zero whenever any o f the three registers are reprogrammed.
ml2722 ds2722 - f - 05 final da tasheet december 2 003 23 register #0, pll con figuration pll charge pump polarity (qpp): db0 this bit sets the charge pump polarity to sink or source current. for a majority of applications, this bit is cleared (qpp = 0). for applications wh ere an external amplifier is in the loop filter, this bit is set to 1 to change the charge pump polarity (see table 7). qpp pll charge pump pola rity 0 frequency signal < frequency reference. charge pump sources current. 1 frequency signal < frequency re ference. charge pump sinks current. table 7. pll charge pump polarity reference divide bit zero (rd0): db1 this bit sets the reference division of the pll to either 6 or 12 (see table 8). rd0 reference division nominal reference fr equency 0 6 6.144 mhz 1 12 12.288 mhz table 8. reference frequency select receive closed loop bit (rxcl): db2 this bit is used in receive mode to put the pll into either open loop or closed loop (see table 9). rxcl receive pll mode 0 pll open loop 1 pll closed loop table 9. pll mode in normal receive operation pll frequency shift bit (lol): db3 lo shift for transmit and receive. for normal operations, it is recommended that lol = 0 (see table 10). lol lo shift for transmi t lo shift for receive 0 0 +1.024 mhz 1 +1.024 mhz 0 table 10. pll frequency shift
ml2722 ds2722 - f - 05 final da tasheet december 2 003 24 transmit closed loop bit (txcl): db4 used to produce a continuous cw transmitter output for product test with rxon low (see table 11). txcl transmit pll mode 0 pll open loop, fsk output 1 pll closed loop, cw output table 11. pll mode in transmit operation transmit power control bit (tpc): db5 controls the state of the tpc/tpq open - drain output (pin 7). although this bit may be set at any time, the tpc/tpq pin only changes state at the falling edge of rxon (see table 12). tpc tpc pin state 0 high impedance 1 pulled to ground table 12. tpc pin state register #1, channel frequency register channel frequency selection bits (chq): these bits set the channel frequency for the transceiver (see table 13). with a 6.1 44mhz or 12.288mhz input to the ref pin (pin 9), the channel frequency value is calculated by multiplying the chq value by 0.512. a 1.024mhz offset is automatically added in the receive mode to accommodate the if frequency. the recommended operating range value of the chq is from 1,024 (400 hex) to 4093 (ffd hex). these bits should be programmed to a valid channel frequency before xcen is asserted. the divide ratio is calculated as f c /0.512, where f c is the channel frequency in mhz. b15 b14 b13 to b2 b1 b0 0 0 pll divide ratio 0 1 table 13. main divider
ml2722 ds2722 - f - 05 final da tasheet december 2 003 25 register #2, filter tuning select test m ode analog test control bits (atm): the test mode selected is described in table 14. the performance of the ml2722 is not specified in these test modes. a lthough primarily intended for ic test and debug, they also can help in debugging the radio system. the default (power - up) state of these bits is atm<2:0> = <0,0,0>. when a non - zero value is written to the field, rssi/tpi (pin 28) and tpc/tpq (pin 7) becom e analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. during normal operation, the atm field should be set to zero. atm2 atm1 atm0 rssi/tpi tpc/tpq 0 0 0 rssi tpc (pa control) 0 0 1 i no connect q no connect 0 1 0 i if buffer output q if buffer output 0 1 1 i if buffer output q if buffer output 1 0 0 i if buffer output q if buffer output 1 0 1 i data slicer input q data slicer input 1 1 0 i if limiter outputs q if limiter outputs 1 1 1 1.67v ref . vco mod. voltage table 14. analog test control bits digital test control bits (dtm): the dtm<2:0> bit functions are described in table 15. the performance of the ml2722 is not specified in these test modes. although primarily intended for ic t est and debug, they also can help in debugging the radio system. the default (power - up) state of these bits is dtm<2:0> = <0,0,0>. when a non - zero value is written to these fields, dout (pin 32) becomes a digital test access port for key digital signals in the transceiver. during normal operation, the dtm field should be set to zero. dtm2 dtm1 dtm0 dout 0 0 0 demodulated data 0 0 1 receiver agc state 0 1 0 pll main divider output 0 1 1 pll reference divider output table 15. digital test control bits tr ansmit and receive d ata interfaces the din and dout cmos logic levels are serial data that correspond to fsk modulated data on the radio channel. the ml2722 operates as an fsk transceiver in the 902 to 928mhz ism band. the chip rate, bit rate and spreading code are controlled by the baseband processor, and the fm deviation and transmit filtering are controlled by the transceiver. din provides data to the transmit data filter, which band limits the transmitted chips or bits before they are fm modulated. the re is no re - timing of the chips or bits, so the transmitted fsk chips or bits take their timing from din (pin 30). in the receive chain, fm demodulation, data filtering, and data slicing take place in the ml2722 receiver, with chip, bit and word rate timin g recovery performed in the baseband processor. rssi and ref there are two other interface pins between the ml2722 transceiver and the baseband ic: the rssi/tpi (pin 28) and ref (pin 9).
ml2722 ds2722 - f - 05 final da tasheet december 2 003 26 ref is the master reference frequency for the transceiver. it supplie s the frequency reference for the rf channel frequency and the filter tuning. the ref pin is a cmos input with internal biasing resistors. it can be ac coupled through a 470pf coupling capacitor to a sine wave source of at least 2.0v peak - to - peak. the pll comparison and the if filter center frequency are both equal to the ref input frequency divided by either 6 or 12, depending on the setting of the rdiv bit in the pll configuration control word. the if filter and data filter bandwidths track the if filter center frequency. the received signal strength indicator (rssi) pin supplies a voltage indicating the amplitude of the received rf signal. it is normally connected to the input of a low - speed adc on an external baseband ic, and is used during channel scann ing to detect clear channels on which the radio may transmit. the rssi voltage is proportional to the logarithm of the received power level. a voltage of 0v to 2.7v typically corresponds to an rf input power of ? 95 to ? 20dbm with a nominal slope of 35mv/db . control outputs to t he pa ? paon and tpc the ml2722 has two output pins to control and sequence the power amplifier ? paon and tpc (see figure 6). figure 6. power amplifier interface the paon (pa control) is a cmos output to control an off - chip rf pa (power amplifier). it outputs a logic high when t he pa should be enabled, and a logic low at all other times. this output is inhibited if the pll fails to lock, or the power supply to the ml2722 falls below 2.6v. the pll lock detect or low voltage signals are latched, so that the transmitter is inhibited for the entire transmit time slot. these latches are reset at the end of the transmit time slot, so that the ml2722 will transmit in the next time slot following a transient fault condition. the tpc/tpq (pin 7) is an open drain output intended for transmi t power control. it is controlled by the tpc bit in serial bus register 0. this bit can be changed at any time, but the tpc pin will not change state until the beginning of the next transmit time slot, triggered by a falling edge on rxon. this pin interfac es to an external pa power control input via a resistor network to set the output power level. in analog test modes the rssi/tpi (pin 28) and tpc/tpq (pin 7) become analog test access ports that allow the user to observe internal signals in the ml2722. rf interfaces the rrfi receive input (pin 21) and the trfo transmit output (pin 23) are the only rf i/o pins. the rrfi pin requires a simple impedance matching network for best input noise figure, and the trfo pin is matched to 50 w by an ac coupling capacitor. the associated rf input and output ground pins must have direct connections to an rf ground plane, and the rf block supply pins must be well decoupled to the rf ground pins. symbol parameter time/ m s t1 rxon falling edge to paon rising edge 62.5 t2 rxon rising edge to pll recalib ration 6.5 t3 rxon rising edge to receive mode 70 t4 rxon rising edge to paon falling edge < 0.1 f s 11 ghz mag angl e 0.9 0.757 - 83.0 rrfi s - parameters at 3.3 v, operating temperatur e 25 o c table 16. typical receive rf input f s 11 ghz mag angle 0.9 0.208 139.5 trfo s - parameters at 3.3 v, operating temperatur e 25 o c table 17. typical transmit rf output t1 t2 t3 t4 rxon internal pllen paon output from trfo
ml2722 ds2722 - f - 05 final da tasheet december 2 003 27 physical dimensions (inches/millimeters) 0.048 max (1.20 max) seating plane 0.354 bsc (9.00 bsc) 0.276 bsc (7.00 bsc) 1 0.276 bsc (7.00 bsc) 0.354 bsc (9.00 bsc) 9 25 17 0.032 bsc (0.8 bsc) pin 1 id 0.012 - 0.018 (0.29 - 0. 45) 0.037 - 0.041 (0.95 - 1.05) 0.018 - 0.030 (0.45 - 0.75) 0.003 - 0.008 (0.09 - 0.20) 0 o - 8 o package: h32 - 7 32 - pin (7 x 7 x 1mm) tqfp leads cannot exceed 0.004 maximum coplanarity (0.102) ordering information part number temper ature range packag e publication ml2722dh ? 10c to 60c 32 pin tqfp 7mm body ds2722 - f - 04
ml2722 ds2722 - f - 05 final da tasheet december 2 003 28 warranty micro linear makes n o representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. the circuits contained in this document are offered as possible applications only. particular uses or applications may invalidate some of t he specifications and/or product descriptions contained herein. the customer is urged to perform its own engineering review before deciding on a particular application. micro linear assumes no liability whatsoever, and disclaims any express or implied warr anty, relating to sale and/or use of micro linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. micro linear products are not designed for use i n medical, life saving, or life sustaining applications. if this document is ?advance?, its contents describe a micro linear product that is currently under development. all detailed specifications including pinouts and electrical specifications may be cha nged without notice. if this document is ?preliminary?, its contents are based on early silicon measurements. typical data is representative of the product but is subject to change without notice. pinout and mechanical dimensions are final. preliminary doc uments supersede all advance documents and all previous preliminary versions. if this document is ?final?, its contents are based on a characterized product, and it is believed to be accurate at the time of publication. final data sheets supersede all prev iously published versions. this document is final. ? 2003 micro linear corporation. all rights reserved. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. paten ts: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. other patents are pending. micro linear corporation 2050 concourse drive san jose, ca 95131 tel: (408) 433 - 5200 fax: (408) 432 - 0295 www.microlinear.com

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